INTEGER to STD_LOGIC_VECTOR

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

conv_std_logic_vector (integer, std_logic_vector_width);

File Decleration difference between VHDL-87 and VHDL-93

http://www.vdlande.com/VHDL/filedec.html

What is wrong in this VHDL code?

ENTITY test IS PORT ( );
END test ;