RANGE DECLERATION IN VHDL

Range cannot be declared for STD_LOGIC_VECTOR types.


CONSTANT ARINC1_ADDR_RNG_L : STD_LOGIC_VECTOR (22 DOWNTO 2) := '1' & X"F0000" ;
CONSTANT ARINC1_ADDR_RNG_H : STD_LOGIC_VECTOR (22 DOWNTO 2) := '1' & X"F1FFF" ;

TYPE ARINC1_ADDR_RNG IS RANGE ARINC1_ADDR_RNG_L TO ARINC1_ADDR_RNG_H ;

Hint: Range must be a scalar type.